Design-Reuse

Using OCP and Coherence Extensions to Support System-Level Cache Coherence

Open Core Protocol (OCP) [1][2] is a common standard for Intellectual Property (IP)core interfaces. OCP facilitates IP core plug-and-play and simplifies reuse by decoupling the cores from the on-chip ...
Semiconductor Engineering

Cache-Coherent Symmetric Multiprocessing With LX8 Controllers On HiFi DSPs

This document motivates the need for a cache-coherent multicore, symmetric multiprocessor (SMP) with applications to embedded control and audio processing. It describes the current state of the art in ...
EDN

Multiprocessor system sports up to four coherent, multi-threaded cores

MIPS32 1004K coherent processing system is a multithreaded, multiprocessor licensable IP multiprocessor platform that supports up to four single- or double-threaded processor cores connected together ...
Design-Reuse

Co-Designed Cache Coherency Architecture for Embedded Multicore Systems

One of the key challenges in chip multi-processing is to provide a programming model that manages cache coherency in a transparent and efficient way. A large number of applications designed for ...
Electronic Design

CCIX: Cache Coherent Interconnect for Accelerators

The Cache Coherent Interconnect for Accelerators standard, or CCIX (pronounced “see 6”), is built on PCI Express (PCIe) to provide a chip-to-chip interconnect for high-speed hardware accelerators. It ...
Electronic Design

Master On-Chip Embedded Multiprocessor Coherence

Without a doubt, embedded systems-on-a-chip (SoCs) are becoming "software-rich," 1 and they're incorporating more and more processors on one chip. The driving forces behind these changes are advances ...