Hackaday

Atomic Clock Trades Receiver For An ESP8266

The advantage of a radio-controlled clock that receives the time signal from WWVB is that you never have to set it again. Whether it’s a little digital job on your desk, or some big analog wall clock ...
Phys.org

Multicore fiber testbed demonstrates precise optical clock signal transmission over 25 km

Researchers have shown, for the first time, that transmission of ultrastable optical signals from optical clocks across tens of kilometers of deployed multicore fiber is compatible with simultaneous ...
Electronic Design

Measuring digital clock stability and jitter with an oscilloscope

Clocks are the heartbeats of embedded systems, providing timing references and synchronization between components, subsystems, and entire systems. Incorrect clock signal amplitudes and timing can ...
Nature

Lighting up the clock rate in electronics

In electronic circuits, data processing is synchronized by a clock signal, which sets the pace for operations. Many modern technologies — from high-speed communications to advanced sensors — depend on ...
Semiconductor Engineering

Clocks Getting Skewed Up

At a logical level, synchronous designs are very simple and the clock just happens. But the clocking network is possibly the most complex in a chip, and it’s fraught with the most problems at the ...
Semiconductor Engineering

The Design Challenges Of Clock Integrity And Clock Jitter

Signal integrity is one of the many challenges faced by chip designers. Deep submicron technologies are unfriendly hosts for the nice, clean signals desired. The culprits that compromise signal ...
Nature

Demonstration of a trapped-ion atomic clock in space

The alternative text for this image may have been generated using AI. The DSAC ion clock, payload configuration and ground testing, as well as its navigational uses and some scientific applications, ...
Microwaves & RF

Clock Spur Suppression in Phased-Array RF Subsystems

RF absorption and PLL phase calibration help phased-array subsystems reduce clock spurs while preserving spectral purity and ...
EDN

SIGNAL CHAIN BASICS #61: Clock jitter demystified-random jitter and phase noise, Part 2

Editor's note: Signal Chain Basics is an ongoing and popular series; click here for a complete, linked list of all installments.) In Signal Chain Basics Part 56 we discussed the fundamental ...
EDN

Mitigate clock intermodulation effects in characterization setups

Mixed-signal printed circuit boards (PCBs) present unique challenges in high-performance applications, such as vibration analysis and other multi-channel data acquisition systems. Nonlinear ...
Electronic Design

Timing Decisions 102: Optimize Your Clock Tree

The importance of timing requirements and jitter budgets for FPGAs, ASICs, and SoCs. How to utilize the information portrayed in a clock tree to choose the most well-suited clock generator for your ...