EDN

Power dissipation in portables: Design considerations using low-power CMOS ICs

When a CMOS circuit is in an idle state there is still some static power dissipation–a result of leakage current through nominally off transistors. Both nMOS and pMOS transistors used in CMOS logic ...
EDN

Power dissipation in high-end integrated communication processors

Static, or “dc,” power refers to power dissipation that occurs as long as the part is on, even if the clocks are off. It is due to the flow of leakage current that occurs in every powered transistor.
Electronic Design

IP Platform Reduces Static And Dynamic Power Dissipation

Promising static and dynamic power dissipation reductions up to 20x and 80%, respectively, the IPrima Mobile application-optimized semiconductor IP platform provides a wide range of power-management ...
Semiconductor Engineering

As Nodes Advance, So Must Power Analysis

Smaller geometry nodes offer cost and performance advantages that encourage their adoption. Yet they present a new set of challenges for IC manufacturers: Though transistors are smaller, they leak ...
Design-Reuse

Virage Logic Introduces Ultra-Low-Power Semiconductor IP Platform, Allowing Up to 20X Reduction in Static, 80 Percent in Dynamic Power Dissipation

IPrima Mobile™ first in family of application-optimized semiconductor IP platforms FREMONT, Calif., June 28, 2004 — One of the unrelenting challenges facing system-on-chip (SoC) designers today is ...
Design-Reuse

Low Power Universal Gates for Approximate Computing

Density and speed of IC’s have increased exponentially for several decades, following a trend described by Moore’s Law. While it is accepted that this exponential improvement trend will end, it is ...
Nature

Current-Mode Logic and Low-Power CMOS Technology

Current-Mode Logic (CML) and low-power Complementary Metal-Oxide-Semiconductor (CMOS) technology continue to drive significant advances in digital circuit design, particularly in high-speed and energy ...