At Semicon West today, Advantest Corp. launched its plans for an industry-wide consortium aimed at solving the challenges of cost effectively testing complex logic devices, such as SOCs. Advantest ...

The clamor for multiple functionalities in next-generation wireless telecom and consumer electronic markets has designers scrambling to adopt a core-based design methodology. However, the lack of ...

More than 40 chips have been licensed to use EFLX eFPGA and >20 chips are working in silicon. Big customers like Renesas are planning high volume families of chips using embedded FPGA. As a result, we ...

Generic test and repair approaches to embedded memory have hit their limit. Smaller feature sizes, such as 130 nm and 90 nm, have made it possible to embed multiple megabits of memory into a single ...

At TOPIC (in the Netherlands) we work every day on high-tech innovations to make the world smarter, healthier, and better. Are you a driven and ambitious Test Architect with a track record to oversee ...

As most ASIC designers are aware, there are two primary test-related issues that cause a high degree of pain and schedule delay in creating ASIC designs — the difficulty in adhering to DFT (Design For ...

Unlock the full InfoQ experience by logging in! Stay updated with your favorite authors and topics, engage with content, and download exclusive resources. In this episode, Thomas Betts chats with ...