Using the DBHitek 0.18 lm process technology, the proposed circuit has the lowest power consumption, power-delay product, and better pumping efficiency compared to the conventional single-ended VBB ...

The lock time of the PLL is very low while the used circuit area is smaller than that of competing technologies. Because of its pure digital nature the C3-PLL-2 does neither require any additional pad ...

Circuit delay is increasingly affected by process variations at lower technology nodes. Global variations are in double digits now, and according to the International Technology Roadmap for ...